Lead Design Verification Engineer

We are seeking a Design Verification Lead to join a well-funded startup whose vision is to bring their energy-efficient programmable processor to market.

This startup has completely thrown out the existing Von-Neumann computation model and are solving problems in a different way with a much more general approach. As opposed to a dedicated accelerator, they use a proprietary ISA conversion using their compiler that lays it out onto a general purpose array.

Responsibilities:Write digital SoC verification plans and scope digital verification development tasks, including the development of functional coverage groups. Manage external digital verification service providers to ensure deadlines are met. Support running gate-level simulations as part of design signoff. Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions. Collect, collate, analyze, and present coverage reports. Work closely with digital designers to determine a strategy to close any coverage gaps. Qualifications:BS in EE or related fields, MS is preferred.2+ years of management experience, strongly preferred that you've led small external teams of verification engineers and/or vendors. Extensive experience writing and maintaining System Verilog test benches and test components. Experience with script development for work automation, preferably with Python. Experience writing custom and reusable verification infrastructure (drivers, monitors, agents, and models).