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Synthesis/STA Engineer

Santa Clara, CA 143,000 – 215,000 USD / yr
Estimated Compensation
143,000 – 215,000 USD / yr

🔒 Direct submission to hiring team • Zero candidate fees

Role & Company Overview

🏢
Employer
Qualcomm
📍
Location / Model
Santa Clara, CA
💼
Employment
Full-Time
🛡️
Recruitment Type
Direct to HR Pipeline
🏭
Industry
General
👥
Company Size
🌐
Headquarters
United States
✈️
Visa & Sponsorship
Global Talent Consideration
✈️
Global Sponsorship Signal: This position is eligible for global talent consideration and work authorization sponsorship for top qualified international candidates.
🛡️
Human-Verified Opening: Inspected by Sarah Jenkins, CIPD • Hirely Editorial Team. Authenticated directly from Qualcomm's hiring pipeline • Zero recruiter markups or candidate fees. Verification Standards

📋 Role Overview & Responsibilities

Company

Qualcomm Atheros, Inc.

Job Area

Engineering Group, Engineering Group > ASICS Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. You will be a part of Qualcomm Connectivity organization responsible for the development of SoC designs.

Roles/Responsibilities

Job responsibilities include RTL Synthesis using state of the art Physical Synthesis Tools; Timing Constraint development for Functional/Test Modes; Timing Constraints integration and validation for the SoC/Sub-Systems; Implement Low Power techniques in Implementation flows; Work with DFT teams to integrate Memory BIST, Scan for Blocks and Sub-Systems; Perform Power Aware Logic Equivalency checks; Run Static Low Power Checks for Isolation/Level Shifter implementations and analyze the results; Implementation of functional ECOs with the help of EDA tools and Validation; Analyze Dynamic and Leakage Power with low power design team and implement various optimization techniques to reduce power.

Lead Static Timing Analysis, work closely with CAD teams on PD STA flow integration and updates; Lead Timing Closure with Automated ECO tools, flows and scripts; Analyze Dynamic and Leakage power on Post Layout database and implement power ecos to reduce it; Lead Timing Sign-off effort to enable Tapeouts on schedule; Develop Automated scripts to analyze the results and improve productivity.

Support Design Verification to enable Gate Level Simulations, Timing Simulations and Power Aware Gate Level Simulations.

Educational Requirements

Bachelor's, Electrical Engineering and/or Computer Engineering or equivalent experience Preferred: Master's, Electrical Engineering and/or Computer Engineering or equivalent experience

Preferred Qualifications

5 years of experience in ASIC Implementation/SynthesisStrong Expertise with Synopsys/Cadence ASIC Synthesis tools and flowsExperience with RTL Coding with Verilog and System VerilogExpertise with LEC/Formality Formal Verification tools, Functional ECO implementation and ValidationExperience with UPF based implementation in Synthesis and PD flowsKnowledgeable in clocking strategies and Create timing constraints for blocks and sub systemsStrong Expertise with PrimeTime (PT) for PreLayout and PostLayout Static Timing AnalysisExperience in Timing Closure with PrimeTime-ECO and/or Tweaker ECO ToolsExposure to RTL and Netlist based Power EstimationsExperience with Memory BIST insertion and Simulations is a plusAutomation skills with Tcl/Python/Perl/Linux scripting languages is a plusGood verbal and written communication skills

Minimum Qualifications

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found here for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay Range

$143,000.00 - $215,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer!

If you would like more information about this role, please contact Qualcomm Careers.

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This position is located in Santa Clara, CA with potential relocation and sponsorship assistance depending on candidate qualifications.

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